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1 of 27 general description the ds28ec20 is a 20480 - bit, 1 - wire ? eeprom organized as 80 memory pages of 256 bits each. an additional page is set aside for control functions. data is written to a 32 - byte scratchpad, verified, and then copied to t he eeprom memory. as a special feature, blocks of eight memory pages can be write protected or put in eprom - emulation mode, where bits can only be changed from a 1 to a 0 state. the ds28ec20 communicates over the single - conductor 1 - wire bus. the communicat ion follows the standard 1 - wire protocol. each device has its own unalterable and unique 64 - bit rom registration number . the registration number is used to address the device in a multidrop 1 - wire net environment. app lications device authentication ieee 1451.4 sensor teds ink/toner cartridges medical sensors pcb identification wireless base stations ordering information part temp range pin - package ds28ec20+ - 40c to +85 c 3 to - 92 ds 28ec20+t - 40c to +85 c 3 to - 92, t &r ds28ec20p+ - 40c to +85 c 6 tsoc ds28ec20p+t - 40c to +85 c 6 tsoc, t&r + denotes a lead (pb) - free /rohs - compliant package. t = t ape and reel . typical operating ci rcuit px.y c v cc i/o ds28ec20 gnd r pup (300 ? to 2.2k ? ) features ? 20480 bits of nonvolatile (nv) eeprom p artitioned into eighty 256- bit pages ? individual 8 - page groups of memory pages (blocks) can be permanently write protected or put in otp eprom - emulation mode ( " write to 0") ? read and write access highly backward - compatible to legacy devices (e.g., ds2433) ? 2 56- bit scratchpad with strict read/write protocols ensures integrity of data transfer ? 200k write/erase cycle endurance at +25c ? unique factory - programmed 64- bit registration number ensures error - free device selection and absolute part identity ? switchpoint hysteresis and filtering to optimize performance in the presence of noise ? communicates to host at 15.4kbps or 90kbps using 1 - wire protocol ? low - cost to- 92 package ? operating range: 5v 5%, - 40c to +85c ? operating range: 3.3v 5%, 0c to +70c (stand ard speed only) ? iec 1000 -4 - 2 level 4 esd protection ( 8kv contact, 15kv air, typical) for i/o pin pin configuration pin 1 ---------- gnd pin 2 ---------- i/o pin 3 ---------- n.c. dallas 28ec20 bot tom view 1 2 3 1 2 3 for tape - and - reel the leads are formed to 100 mils (2.54mm) spacing versus 50 mils (1.27mm) for bulk. tsoc, top view 1 2 3 6 5 4 pin 1 ---------- n.c. pin 2 ---------- i/o pin 3 ---------- gnd pin 4, 5, 6 ---- n.c. to - 92 commands, bytes, and modes are capitalized for clarity. 1 - wire is a registered trademark of maxim integrated products, inc. ds28ec20 20kb 1 - wire eeprom 19 - 6067 ; rev 4 ; 3 / 12
ds28ec20: 20kb 1 - wire eeprom 2 of 24 absolute maximum rat ings i/o voltage to gnd - 0.5v, +6v i/o sink current 20ma operating temperature ran ge - 40c to +85c junction temperature +150c storage temperature range - 55c to +125c lead temperature (soldering, 10s) +300 c soldering temperature (reflow) to - 92 +250 c tsoc +260 c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. 5.0v supply electri cal characteristics (v pup = 5.0v 5%, t a = - 40c to +85c, unless otherwise noted.) ( note 1 ) parameter symbol conditions min typ max units i/o pin general data 1 - wire pullup resistance r pup (notes 2, 3) 0.3 2.2 k ? input capa citance c io (notes 4, 5) 2000 pf input load current i l i/o pin at v pup 0.05 3.5 a high - to - low switching threshold v tl (notes 5, 6, 7) 1.6 v pup - 1.8 v input low voltage v il (notes 2, 8) 0.5 v low - to - high switching threshold v th (notes 5 , 6, 9) 2.5 v pup - 1.1 v switching hysteresis v hy (notes 5, 6, 10) 0.30 1.30 v output low voltage v ol at 4ma (note 11) 0.20 v recovery time (notes 2, 12) t rec standard speed 5 s overdrive speed 5 rising - edge hold - off time (notes 5, 13) t r eh standard speed 0.5 5.0 s overdrive speed not applicable (0) timeslot duration (notes 2, 14) t slot standard speed 65 s overdrive speed 11 i/o pin, 1 - wire reset, presence dete ct cycle reset - low time (note 2) t rstl standard speed 480 640 s overdrive speed 48 80 presence - detect high time t pdh standard speed 15 60 s overdrive speed 2 6 presence - detect low time t pdl standard speed 60 240 s overdrive speed 8 24 presence - detect sample time (notes 2, 15) t msp stan dard speed 60 75 s overdrive speed 6 10 i/o pin, 1 - wire write write - 0 low time (notes 2, 16, 17) t w0l standard speed 60 120 s overdrive speed 6 15.5 write - 1 low time (notes 2, 17) t w1l standard speed 1 15 s overdrive speed 1 2 i/o pin, 1 - wire read read - low time (notes 2, 18) t rl standard speed 5 15 - s overdrive speed 1 2 - read - sample time (notes 2, 18) t msr standard speed t rl + 15 s overdrive speed t rl + 2
ds28ec20: 20k b 1- wire eeprom 3 of 27 parameter symbol conditions min typ max units eeprom programming current i prog (not e 19) 0.9 ma programming time t prog (note 20) 10 ms write/erase cycles (endurance) (notes 21, 22) n cy at +25c 200k ? at +85c (worst case) 50k data retention (notes 23, 24, 25) t dr at +85c (worst case) 40 years note 1: limits are 100% production tested at t a = +25 c and/or t a = +85 c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1 - w ire d evices in the system, 1 - wire recovery times, and current requirements during eeprom programming. the specified value here applies to systems with only one device and with the minimum 1 - wire recovery times. for more heavily loaded systems, an active pullup such as that found in the ds2482 - x00, ds2480b, or ds2490 may be required. note 4: typical value represents the internal parasite capacitance when v p up is first applied. once the parasite capacitance is charged, it does not affect normal communication. note 5: guaranteed by design, characterization and/or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage which is itse lf a function of v pup , r pup , 1 - wire timing, and capacitive loading on i/o. lower v p up , higher r p up , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on i/o, a lo gic 0 is detected. note 8: the voltage on i/o needs to be less or equal to v ilmax at all times the master is driving i/o to a logic 0 level. note 9: voltage above which, during a rising edge on i/o, a logic 1 is detected. note 10: after v th is crossed during a rising edge on i/o, the voltage on i/o has to drop by at least v hy to be detected as logic 0. note 11: the i - v characteristic is approximately linear for voltages less than 1v. note 12: applies to a single device attached to a 1 - wire line. no te 13: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to 1/(t w0l min + t recmin ). note 15: interval after t rstl during which a bus master can read a logic 0 on i/o if there is a ds28ec20 present. the power - up presence detect pulse could be outside this interval but will be complete within 2ms after power - up. note 16: highlighted numbers are not in compliance with legacy 1 - wire product standards. see comparison table bel ow. note 17: in figure 11 represents the time required for the pullup circuitry to pull the voltage on i/o up from v il to v th . the actual maximum duration for the master to pull the line low is t w1l max + t f - and t w0l max + t f - , respectively. note 18: in figure 11 represents the time required for the pullup circuitry to pull the voltage on i/o up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 19: current drawn from i/o during the eeprom programming interval. during a programming cycle the voltage at i/o drops by i prog r p up below v p up . if v p up and r p up are within their ec table limits, the residual i/o voltage meets the guaranteed -by - design minimum volta ge requirements for programming. note 20: the t prog interval begins t re hmax after the trailing rising edge on i/o for the last time slot of the e/s byte for a valid copy scratchpad sequence. interval ends once the device's self - timed eeprom programming cy cle is complete and the current drawn by the device has returned from i prog to i l . note 21: write - cycle endurance is degraded as t a increases. note 22: not 100% production - tested; guaranteed by reliability monitor sampling. note 23: data retention is de graded as t a increases. note 24: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sh eet limit at operating temperature range is established by reliability testing. note 25: eeprom writes may become nonfunctional after the data retention time is exceeded. long - time storage at elevated temperatures is not recommended; the device may lose its write capability after 10 years at +125c or 40 years at +85c. legacy values ds28ec20 valu es parameter standard speed overdrive speed# standard speed overdrive speed# min max min max min max min max t slot (incl. t rec ) 61s (undefined) 7s (undefined) 65s* (undefined) 11s (undefined) t rstl 480s (undefined) 48s 80s 480s 640s 48s 80s t pdh 15s 60s 2s 6s 15s 60s 2s 6s t pdl 60s 240s 8s 24s 60s 240s 8s 24s t w0l 60s 120s 6s 16s 60s 120s 6s 15.5s * intentional change, longer recovery time requirement due to modified 1 - wire front - end. # for operation at overd rive speed, the ds28ec20 requires v pup to be 5v 5%.
ds28ec20: 20k b 1- wire eeprom 4 of 27 3.3v supply electrical characteristics (v pup = 3.3v 5%, t a = 0c to +70c, unless otherwise noted. ) parameter symbol conditions min typ max units i/o pin general data 1 - wire pull up resistance r pup (notes 1, 2) 0.3 2.2 k ? input capacitance c io (notes 3, 4) 2000 pf input load current i l i/o pin at v pup 0.05 3.5 a high - to - low switching threshold v tl (notes 4, 5, 6) 0.49 v pup - 1.9 v input low voltage v il (notes 1, 7) 0.5 v low - to - high switching threshold v th (notes 4, 5, 8) 1.09 v pup - 1.1 v switching hysteresis v hy (notes 4, 5, 9) 0.33 0.70 v output low voltage v ol at 4ma (note 10) 0.30 v recovery time t rec standard speed (notes 1, 11) 5 s rising - edg e hold - off time t reh standard speed (notes 4, 12) 0.5 5.0 s timeslot duration t slot standard speed (notes 1, 13) 65 s i/o pin, 1 - wire reset, presence dete ct cycle reset - low time t rstl standard speed (note 1) 480 640 s presence - detect high time t pdh standard speed 15 60 s presence - detect low time t pdl standard speed 60 240 s presence - detect sample time t msp standard speed (notes 1, 14) 60 75 s i/o pin, 1 - wire write write - 0 low time t w0l standard speed (notes 1, 15) 60 120 s write - 1 low time t w1l standard speed (notes 1, 15) 1 15 s i/o pin, 1 - wire read read - low time t rl standard speed (notes 1, 16) 5 15 - s read - sample time t msr standard speed (notes 1, 16) t rl + 15 s eeprom programming current i prog (no te 17) 0. 9 ma programming time t prog (note 18) 10 ms write/erase cycles (endu - rance) (notes 19, 20) n cy at +25c 200k ? at +70c 50k data retention t dr (notes 21, 22, 23) 40 years
ds28ec20: 20k b 1- wire eeprom 5 of 27 note 1 : system requirement. note 2: maximum allowa ble pullup resistance is a function of the number of 1 - wire devices in the system, 1 - wire recovery times, and current requirements during eeprom programming. the specified value here applies to systems with only one device and with the minimum 1 - w ire recov ery times. for more heavily loaded systems, an active pullup such as that found in the ds2482 - x00, ds2480b, or ds2490 may be required. note 3: typical value represents the internal parasite capacitance when v p up is first applied. once the parasite capacitance is charged, it does not affect normal communication. note 4: guaranteed by design, characterization and/or simulation only. not production tested. note 5: v tl , v th , and v h y are a function of the internal supply voltage which is itself a function of v pup , r pup , 1 - wire timing, and capacitive loading on i/o. lower v p up , higher r p up , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . no te 6: voltage below which, during a falling edge on i/o, a logic 0 is detected. note 7: the voltage on i/o needs to be less or equal to v ilmax at all times the master is driving i/o to a logic 0 level. note 8: voltage above which, during a rising edge o n i/o, a logic 1 is detected. note 9: after v th is crossed during a rising edge on i/o, the voltage on i/o has to drop by at least v hy to be detected as logic 0. note 10: the i - v characteristic is approximately linear for voltages less than 1v. note 1 1: applies to a single device attached to a 1 - wire line. note 12: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 13: defines maximum possible bit rate. equal to 1/(t w0l min + t recmin ). note 14: interval after t rstl during which a bus master can read a logic 0 on i/o if there is a ds28ec20 present. the power - up presence det ect pulse could be outside this interval but will be complete within 2ms after power - up. note 15: in figure 11 represents the time required for the pullup circuitry to pull the voltage on i/o up from v il to v th . the actual maximum duration for the master to pull the line low is t w1l max + t f - and t w0l max + t f - , respectively. note 16: in figure 11 represents the time required for the pu llup circuitry to pull the voltage on i/o up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 17: current drawn from i/o during the eeprom programming interval. th e pullup circuit on i/o during the programming interval should be such that the voltage at i/o is greater than or equal to 3.0v . for 3.3v5% v p up operation of the ds28ec20, a low - impedance bypass of r p up , which can be activated during programming, i s required. note 18: the t prog interval begins t re hmax after the trailing rising edge on i/o for the last time slot of the e/s byte for a valid copy scratchpad sequence. interval ends once the device's self - timed eeprom programming cycle is complete and t he current drawn by the device has returned from i prog to i l . note 19: write - cycle endurance is degraded as t a increases. note 20: not 100% production - tested; guaranteed by reliability monitor sampling. note 21: data retention is degraded as t a increase s. note 22: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sh eet limit at operating temperature range is established by reliability testing. note 23: eeprom writes may become non functional after the data retention time is exceeded. long - time storage at elevated temperatures is not recommended; the device may lose its write capability after 10 years at +125c or 40 years at +85c.
ds28ec20: 20k b 1- wire eeprom 6 of 27 pin description name function i/o 1 - wire bus in terface. open drain, requires external pullup resistor. gnd ground reference n.c. not connected description the ds28ec20 combines 20kb of data eeprom with a fully featured 1 - wire interface in a single chip. the memory is organized as 80 pages of 256 bits each. in addition, the device has one page for control functions such as permanent write protection and eprom - emulation mode for individual 2048- bit (8- page) memory blocks . a volatile 256 - bit memory page called the scratchpad acts as a buffer when wri ting data to the eeprom to ensure data integrity. data is first written to the scratchpad, from which it can be read back for verification before transferring it to the eeprom. the operation of the ds28ec20 is controlled over the single - conductor 1- wire bu s. device communication follows the standard 1 - wire protocol. the energy required to read and write the ds28ec20 is derived entirely from the 1 - wire communication line. each ds28ec20 has its own unalterable and unique 64 - bit registration number. the regist ration number guarantees unique identification and is used to address the device in a multidrop 1 - wire net environment. multiple ds28ec20 devices can reside on a common 1 - wire bus and be operated independently of each other. applications of the ds28ec20 in clude device authentication, analog - sensor calibration such as ieee - p1451.4 smart sensors teds, ink and toner print cartridge identification, medical - sensor calibration data storage, pc board identification, and data for self - configuration of central offic e switches, wireless base stations, pbxs, or other modular - based rack systems. the ds28ec20 provides a high degree of backward compatibility with the ds2433. besides the different family codes, the only protocol change that is required on an existing ds243 3 implementation is a lengthening of the programming duration (t prog ) from 5ms to 10ms. figure 1. block diagram i / o 64 - b it registration # 1 - wire function control memory function control unit parasit e power 32 - byte scratchpad data memory 80 pages of 32 bytes each crc16 generator special function registers ds28ec20
ds28ec20: 20k b 1- wire eeprom 7 of 27 overview the block diagram in figure 1 shows the relationships between the major control and memory sections o f the ds28ec20. the ds28ec20 has four main data components: 1) 64 - bit registration number, 2) 32- byte scratchpad, 3) eighty 32 - byte pages of eeprom, and 4) special function registers. the hierarchical structure of the 1- wire protocol is shown in figure 2. the bus master must first provide one of the seven rom (network) function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom, 5) resume, 6) overdrive skip rom, or 7) overdrive match rom. upon completion of an overdrive rom command byte execute d at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. for operation at overdrive speed, the ds28ec20 requires v pup to be 5v 5%. the protocol required for these rom function commands is described in figure 9. after a rom function command is successfully executed, the memory functions become accessible and the master may provide any one of the five memory function commands. the protocol for these commands is described in figure 7. all data is read and written least significant bit first. figure 2. hierarchical structure for 1 - wire protocol ds28ec20 command level: 1 - wire rom function commands (see figure 9) ds28ec20 - specific memory function commands (see figure 7) available commands: data field affected: read rom match rom search rom skip rom resume overdrive skip* overdrive match* 64 - bit reg. #, rc - flag 64 - bit reg. #, rc - flag 64 - bit reg. #, rc - flag rc - flag rc - flag rc - flag, od - flag 64 - bit reg. #, rc - flag, od - flag write scratchpad read scratchpad copy scratchpad read memory extended read mem. 32 - byte scratchpad, flags 32 - byte scratchpad data memory, regis ter page data memory, register page data memory, register page * for operation at overdrive speed, the ds28ec20 requires v pup to be 5v 5%. 64 - bit rom each ds28ec20 contains a unique r om code that is 64 bits long. the first 8 bits are a 1 - wire family code. the next 48 bits are a unique serial number. the last 8 bits are a cyclic redundancy check (crc) of the first 56 bits. see figure 3 for details. the 1 - wire crc is generated using a po lynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1 - wire crc is available in application note 27 : understanding and using cyclic redundancy checks with maxim i button ? products ( www.maxim - ic.com/an27 ). the shift register bits are initialized to 0. then, starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the last bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of the crc returns the shift register to all 0s. figure 3. 64 - bit rom msb l sb 8 - bit crc code 48- bit serial number 8 - bit family code (43h) msb lsb msb lsb msb lsb i button is a registered trademark of maxim inte grated products, inc.
ds28ec20: 20k b 1- wire eeprom 8 of 27 figure 4. 1 - wire crc generator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data memory data memory and special function registers are located in a linear address space, as shown in figure 5. the data memory and the registers have unrestricted read access. the data memory consists of 80 pages of 32 bytes each. eight adjacent pages form one 2kb block . each block can be individually set to open (default), write protected, or eprom m ode by setting the associated protection byte in the register page, which starts at address 0a00h. besides the 10 block protection control bytes (one for each 2kb data memory block) the register page contains 20 bytes of user eeprom plus a memory block loc k byte and a register page lock byte. starting at address 0a20h, the ds28ec20 has a read - only memory page that stores a factory byte and a 2- byte field reserved for a factory - administered service to program manufacturer identification. all other bytes of t hat page are reserved. the manufacturer id can be a customer - supplied identification code that assists the application software in identifying the product the ds28ec20 is associated with. contact the factory to set up and register a custom manufacturer id. in addition to the eeprom, the device has a 32 - byte volatile scratchpad. writes to the eeprom array are a two- step process. first, data is written to the scratchpad, and then copied into the main array. the user can verify the data in the scratchpad prior to copying. the protection control registers, along with the memory block lock byte, determine whether write protection, eprom mode, or copy protection is enabled for each of the 10 data memory blocks. a value of 55h sets write protection for the associ ated memory block. a value of aah sets eprom mode. the memory block lock byte, if programmed to either 55h or aah, sets copy protection for all write - protected data memory blocks. blocks in eprom mode are not affected. programming the register page lock by te to either 55h or aah copy protects the entire register page. the protection control registers and the lock bytes write protect themselves if set to 55h or aah. any other setting leaves them open for unrestricted write access. see the copy protection sec tion for explanation of copy protect vs. write protect. write protection: write protection prevents data from being changed, but does not block the copy - scratchpad function; this allows the memory to be reprogrammed with the same data. in eeprom devices d igital information is stored as electrical charge (electrons) on floating gates. quantum mechanical effects allow electrons to be transported in large numbers to and from the floating gate for programming and erasing memory cells. electrons leave the float ing gate at a temperature - dependent rate. the higher the temperature, the faster is the rate at which electrons escape. this rate is expressed as data retention in the ec table. reprogramming the memory returns the charge to the original value for a full d ata retention time. this is particularly useful in applications where data retention is a concern, e.g., at high temperatures. copy protection: copy protection blocks the execution of the copy - scratchpad function. this feature achieves a higher level of s ecurity, and should only be used after all write - protected locations and their associated protection control bytes are set to their final values. copy protection does not prevent copying data from one device to another.
ds28ec20: 20k b 1- wire eeprom 9 of 27 figure 5. memory map address range type description protection codes (no tes) 0000h to 00ffh r/(w) data memory pages 0 to 7 (block 0) (protection controlled by address 0a00h) 0100h to 01ffh r/(w) data memory pages 8 to 15 (block 1) (protection controlled by address 0a01h) 0200h to 02ff h r/(w) data memory pages 16 to 23 (block 2) (protection controlled by address 0a02h) 0300h to 03ffh r/(w) data memory pages 24 to 31 (block 3) (protection controlled by address 0a03h) 0400h to 04ffh r/(w) data memory pages 32 to 39 (block 4) (protect ion controlled by address 0a04h) 0500h to 05ffh r/(w) data memory pages 40 to 47 (block 5) (protection controlled by address 0a05h) 0600h to 06ffh r/(w) data memory pages 48 to 55 (block 6) (protection controlled by address 0a06h) 0700h to 07ffh r/(w) data memory pages 56 to 63 (block 7) (protection controlled by address 0a07h) 0800h to 08ffh r/(w) data memory pages 64 to 71 (block 8) (protection controlled by address 0a08h) 0900h to 09ffh r/(w) data memory pages 72 to 79 (block 9) (protection con trolled by address 0a09h) 0a00h* to 0a09h* r/(w) protection control blocks 0 to 9 55h: write protected; aah: eprom mode. address 0a00h is associated with block 0, address 0a01h with block 1, etc. 0a0ah to 0a1dh r/(w) user eeprom (protection controlled by address 0a1fh) 0a1eh* r/(w) memory block lock (see text) 0a1fh* r/(w) register page lock (see text) 0a20h r factory byte (55h ? no valid manufacturer id, aah ? 0a23h to 0a24h are a valid manufacturer id) 0a21h to 0a22h r factory trim bytes (unsp ecified value) 0a23h to 0a24h r manufacturer id validity depends on factory byte 0a25h to 0a3fh r reserved (unspecified value) * once programmed to aah or 55h this address becomes read - only. all other codes can be stored but neither write- protect the address nor activate any function.
ds28ec20: 20k b 1- wire eeprom 10 of 27 address registers an d transfer status the ds28ec20 employs three address registers: ta1, ta2, and e/s (figure 6). registers ta1 and ta2 must be loaded with the target address to which the data is written or from which da ta is read. register e/s is a read - only transfer status register used to verify data integrity with write commands. e / s bits e[4:0] are loaded with the incoming t[4:0] on a write scratchpad command and increment on each subsequent data byte. this is, in ef fect, a byte - ending offset counter within the 32- byte scratchpad. bit 5 of the e/s register, called pf, is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of powe r. a valid write to the scratchpad clears the pf bit. bit 6 has no function; it always reads 0. the highest valued bit of the e/s register, called authorization accepted (aa), is valid only if the pf flag reads 0. if pf is 0 and aa is 1, the data stored in the scratchpad has already been copied to the target memory address. writing data to the scratchpad clears this flag. figure 6. address registers bit # 7 6 5 4 3 2 1 0 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t 14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa 0 pf e4 e3 e2 e1 e0 writing with verific ation to write data to the ds28ec20 , the scratchpad must be used as intermediate storage. first, the master issues the writ e scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. under certain conditions (see the write scratchpad command section) the master receives an inverted crc16 of the command, address (actual addr ess sent), and data at the end of the write scratchpad command sequence. knowing this crc value, the master can compare it to the value it has calculated itself to decide if the communication was successful and precede to the copy scratchpad command. if th e master could not receive the crc16, it should send the read scratchpad command to verify data integrity. as a preamble to the scratchpad data, the ds28ec20 repeats the target address ta1 and ta2 and sends the contents of the e/s register. if the pf flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. the master does not need to continue reading; it can start a new trial to write data to the scratchpad. similarly, a set aa flag together with a cleared pf flag indicates that the device did not recognize the write command. if everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. now the master can continue reading and verifying every data byte. after the master has verified the data, it can send the copy scratchpad command, for example. this command must be followed exactly by the data of the three address registers ta1, ta2, and e/s. the master should obtain the contents of these registers by reading the scratchpad. as soon as the ds28ec20 has received these bytes correctly, it starts copying the scratchpad data to the requested location, provided that the target memory is not copy protected, th e pf flag is cleared, and there was no read memory or extended read memory command issued between write scratchpad and copy scratchpad.
ds28ec20: 20k b 1- wire eeprom 11 of 27 memory function comm ands the memory function flow c hart (figure 7) describes the protocols necessary for accessing th e memory of the ds28ec20. the target address registers ta1 and ta2 are used for both read and write. to prevent accidental changes to the data memory or control registers the device employs a bs - flag indicating a bad sequence. the communication between m aster and ds28ec20 takes place either at standard speed (default, od = 0) or at overdrive speed (od = 1). if not explicitly set into the overdrive mode, the ds28ec20 assumes stan dard speed. for operation at overdrive speed, the ds28ec20 requires v pup to b e 5v 5%. write scratchpad com mand [0f h] the write scratchpad command applies to the data memory and the writable addresses in the register page. after issuing the write scratchpad command, the master must first provide the 2 - byte target address, followe d by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte offset of t[4:0]. the e/ s bits e[4:0] are loaded with the starting byte offset, and increment with each subsequent byte. effectively, e[4:0] is the by te offset of the last full byte written to the scratchpad. only full bytes are accepted. if the last byte is incomplete its content is ignored and the partial byte flag pf is set. the pf flag is also set if the master ends the command before a complete tar get address is transmitted. the pf and bs flags are both cleared when a complete target address is received. when executing the write scratchpad command, the crc generator inside the ds28ec20 (figure 13) calculates a 16- bit crc of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. this crc is generated using the crc16 polynomial (x 16 + x 15 + x 2 + 1) by first clearing the crc generator and then shifting in the command code (0fh) of the write scratchp ad command, the target addresses ta1 and ta2 as supplied by the master, and all the data bytes. the master can end the write scratchpad command at any time. however, if the end of the scratchpad is reached (e[4:0] = 11111b), the master can send 16 read - tim e slots to receive the crc generated by the ds28ec20. if a write scratchpad is attempted to a write - protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. similarly, if the target address page is in eprom mode, the scratchpad is loaded with the bitwise logical and of the transmitted data and the data already in memory. the ds28ec20s memory address range is 0000h to 0a3fh. if the bus master sends a target address higher than this, the ds28ec20s int ernal circuitry sets the four most significant address bits to zero as they are shifted into the internal address register. the read scratchpad command reveals the modified target address. the master identifies such address modifications by comparing the t arget address read back to the target address transmitted. if the master does not read the scratchpad, a subsequent copy scratchpad command does not work since the most significant bits of the target address the master sends do not match the value the ds28 ec20 expects. read scratchpad comm and [aa h] the read scratchpad command allows verifying the target address and the integrity of the scratchpad data. after issuing the command code, the master begins reading. the first two bytes are the target address. t he next byte is the ending offset/data status byte (e/s) followed by the scratchpad data beginning at the byte offset (t[4:0]). the scratchpad data can be different from what the master originally sent. this is of particular importance if the target addres s is within the register page or a page in either write protection or eprom modes. see the write scratchpad command section for details. the master should read through the end of the scratchpad, after which it receives an inverted crc16, based on data as i t was sent by the ds28ec20 . if the master continues reading after the crc, all data are logic 1s.
ds28ec20: 20k b 1- wire eeprom 12 of 27 figure 7 - 1. memory function flow c hart 0fh write scratch - pad ? bus master tx eeprom array target address ta1 (t[7:0]), ta2 (t[15:8]) y n to figure 7, 2 nd part from figure 7, 2 nd part bus master tx memory function command to rom functions flow chart (figure 9) from rom functions flow chart (figure 9) master tx reset ? master tx data byte to scratchpad offset n y ds28ec20 sets scratch - pad offset = (t[4:0]), clears pf, aa, bs scrpad. offset = 11111b? ds28ec20 tx crc16 of command, address, data bytes as they were sent by the bus master ds28ec20 increments scratchpad offset master tx reset? y n bus master rx 1 s n partial byte ? pf = 1 y n y if the memory is write - protected , the ds28ec20 copies the data byte from the target address into the scratchpad. if the memory is in eprom mode , the ds28ec20 stores the bitwise logical and of the transmitted byte and the data byte from the targeted address into the scratchpad. ds28ec20 sets (e[4:0]) = scratchpad offset note : the pf flag is set upon power - on reset. it is cleared only if a com - plete 16 - bit target address is trans - mitted. send ing less than 16 bits for the target address sets the pf flag.
ds28ec20: 20k b 1- wire eeprom 13 of 27 figure 7 - 2. memory function flow c hart (continued) aah read scratch - pad ? ds28ec20 sets scratch - pad offset = (t[4:0]) bus master rx ta1 (t[7:0]), ta2 (t[15:8]) and e/s byte bus master rx data byte from scratchpad offset y bus master rx 1s master tx reset ? y n master tx reset ? ds28ec20 increments scra tchpad offset scrpad. offset = 11111b ? y y n n n from figure 7, 1 st part to figure 7, 1 st part to figure 7, 3 rd part from figure 7, 3 rd part see note in write scratchpad flow chart for additional details. bus master rx crc16 of command, address, e/s byte, data bytes as sent by the ds28ec20
ds28ec20: 20k b 1- wire eeprom 14 of 27 figure 7 - 3. memory function flow c hart (continued) from figure 7, 2 nd part to figure 7, 2 nd p art to figure 7, 4 th part from figure 7, 4 th part * 1 - wire idle high for t prog for power 55h copy scratch - pad ? bus master tx ta1 (t[7:0]), ta2 (t[15:8]) and e/s byte y n bus master rx 1s master tx reset ? y n y auth. code match ? n ds28ec20 copies scratch - pad data to address aa = 1 * d s28ec20 tx 0 master tx reset ? master tx reset ? y n ds28ec20 tx 1 n y n copy - protected ? y y n pf = 0? y n bs = 0?
ds28ec20: 20kb 1-wire eeprom 15 of 27 figure 7-4. memory functi on flowchart (continued) f0h read memory ? y n from figure 7, 3 rd part to figure 7, 3 rd part a5h extended read memory? n y bus master tx ta1 (t[7:0]), ta2 (t[15:8]) ds28ec20 sets memory address = (t[15:0]) ds28ec20 increments address counte r bus master rx ?1?s address < 0a3fh? y n n master tx reset? y master tx reset? bus master rx data byte from memory address y n n bus master rx ?1?s master tx reset ? y ds28ec20 sets memory address = (t[15:0]) bus master tx ta1 ( t[7:0]), ta2 (t[15:8]) decision made by ds28ec20 decision made by master master rx byte from memory address address <0a40h master tx reset? ds28ec20 increments address counte r end of page? master tx reset n y n y crc ok? y n y n master rx ffh byte master rx crc16 of command, address, data (1 st pass); crc16 of data (subsequent passes) bs = 1 bs = 1
ds28ec20: 20k b 1- wire eeprom 16 of 27 copy scratchpad [55 h] the copy scratchpad command is used to copy data from the scratchpad to the d ata memory and the writable sections of the register page. after issuing the copy scratchpad command, the master must provide a 3 - byte authorization pattern, which should have been obtained by an immediately preceding read scratchpad command. this 3 - byte p attern must exactly match the data contained in the three address registers (ta1, ta2, e/s, in that order). if the pattern matches, the target address is valid, the pf and bs flag are not set, and the target memory is not copy protected, the aa flag is set and the copy begins. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. anywhere from 1 to 32 bytes can be copied with this command. the duration of the devices internal data transfer is t prog during which the 1 - wire bus must be idle or actively pulled high. active pullup is optional for this device. a pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. if the pf flag or bs flag is set or the target memory is copy protected, the copy does not begin and the aa flag is not set. the bs flag ensures that copy scratchpad is not executed (blocked) if there was a read memory or extended read memory between write scratchpad and copy scratchpad. read memory [f0 h] the read memory command is the general function to read from the ds28ec20 . after issuing the command, the master must provide a 2 - byte target addres s, which should be in the range of 0000h to 0a3fh. if the target address is higher than 0a3fh, the ds28ec20 changes the upper four address bits to 0. after the address is transmitted, the master reads data starting at the (modified) target address and can continue until address 0a3fh. if the master continues reading, the result is ffh. the read memory command sequence can be ended at any point by issuing a reset pulse. note that this command sets the bs flag. this requires any scratchpad data to be re written before it can be used in a copy scratchpad sequence. extended read memory [a5 h] this command works essentially the same way as read memory, except for the 16 - bit crc that the ds28ec20 generates and transmits following the last data byte of a memory page. the crc generated by this command uses the same polynomial as the write scratchpad command. after issuing the command, the master must provide a 2 - byte target address, which should be in the range of 0000h to 0a3fh. if the target address is higher than 0a3fh, the ds28ec20 changes the upper four address bits to 0. after the address is transmitted, the master reads data starting at the (modified) target address and continuing until the end of a 32 - byte page is reached. at that point the bus master receives an inverted 16 - bit crc. if the master continues reading it receives data starting at the begin- ning of the next page, followed again by the inverted crc for that page. reading beyond the end of the memory is permissible, but the result is ffh. the extended read memory command sequence can be ended at any point by issuing a reset pulse. note that this command sets the bs flag. this requires any scratchpad data to be r e written before it can be used in a copy scratchpad sequ ence. 1- wire bus system the 1 - wire bus is a system that has a single bus master and one or more slaves. in all instances the ds28ec20 is a slave device. the bus master is typically a microcontroller. the discuss ion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1 - wire signaling (signal types and timing). the 1 - wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. hardware configurati on the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate thi s, each device attached to the 1 - wire bus must have open - drain or tri - state outputs. the 1 - wire port of the ds28ec20 is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1 - wire bus with multiple slave s attached. the ds28ec20 supports both a standard and overdrive communication speed of 15.4kbps (max) and 90kbps (max), respectively. for operation at overdrive
ds28ec20: 20k b 1- wire eeprom 17 of 27 speed, the ds28ec20 requires v pup to be 5v 5%. note that legacy 1 - wire products suppor t a standard communication speed of 16.3kbps and overdrive of 142kbps. the slightly reduced rates for the ds28ec20 are a result of additional recovery times, which in turn were driven by a 1 - wire physical interface enhancement to improve noise immunity. th e value of the pullup resistor primarily depends on the network size and load conditions. the ds28ec20 requires a pullup resistor of 2.2k ? (max) at any speed. the idle state for the 1 - wire bus is high. if for any reason a transaction needs to be suspende d, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 16s (overdrive speed) or more than 120s (standard speed), one or more devices on the bus can be reset. figure 8. h ardware configuration open - drain port pin rx = receive tx = transmit 100 ? mosfet v pup rx tx tx rx data r pup i l bus master ds28ec20 1 - wire port transaction sequence the protocol for accessing the ds28ec20 through the 1 - wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction/data initialization all tran sactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know tha t the ds28ec20 is on the bus and is ready to operate. for more details, see the 1 - wire signaling section. 1- wire rom function commands once the bus master has detected a presence, it can issue one of the seven rom function commands that the ds28ec20 suppo rts. all rom function commands are 8 bits long. see figure 9 for list of these commands. read rom [33 h] this command allows the bus master to read the ds28ec20s 8 - bit family code, unique 48- bit serial number, and 8 - bit crc. this command can only be used if there is a single slave on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired - and result). the resultant family code and 48 - bit serial number resul t in a mismatch of the crc.
ds28ec20: 20k b 1- wire eeprom 18 of 27 match rom [55 h] the match rom command, followed by a 64 - bit rom sequence, allows the bus master to address a specific ds28ec20 on a multidrop bus. only the ds28ec20 that exactly matches the 64 - bit rom sequence responds to the fo llowing memory function command. all other slaves wait for a reset pulse. this command can be used with a single or multiple devices on the bus. search rom [f0 h] when a system is initially brought up, the bus master might not know the number of devices on the 1 - wire bus or their registration numbers. by taking advantage of the buss wired - and property, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the registration number, starting wit h the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the second slot, each slave device participating in the s earch outputs the complemented value of its registration number bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the rom code tree. after one complete pass, the bus master knows the registration number of a sin gle device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1 - wire search algorithm ( www.maxim - ic.com/an187 ) for a detailed discussion, including an example. skip rom [cch] this command can save time in a single - drop bus system by allowing the bus master to access the memory functions without providing the 64 - bit rom code. if more than one slave is present on the bus and, for example, a read command is issued following the skip rom command, data collision occurs on the bus as multiple slaves transmit simultaneously (open - drain pulldowns produce a wired- and result). resume [a5h] to maximize the data throughput in a multidrop environment, the resume fu nction is available. this function checks the status of the rc bit and, if it is set, directly transfers control to the memory functions, similar to a skip rom command. the only way to set the rc bit is through successfully executing the match rom, search rom, or overdrive match rom command. once the rc bit is set, the device can repeatedly be accessed through the resume command function. accessing another device on the bus clears the rc bit, preventing two or more devices from simultaneously responding to the resume command function. overdrive skip rom [ 3c h]* on a single - drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64 - bit rom code. unlike the normal skip rom command, the overdrive skip rom sets the ds28ec20 in the overdrive mode (od = 1). all communication following this command must occur at overdrive speed until a reset pulse of minimum 480s duration resets all devices on the bus to standard speed (od = 0). when issued on a multidro p bus, this command sets all overdrive - supporting devices into overdrive mode. to subsequently address a specific overdrive - supporting device, a reset pulse at overdrive speed must be issued followed by a match rom or search rom command sequence. this spee ds up the time for the search process. if more than one slave supporting overdrive is present on the bus and the overdrive skip rom command is followed by a read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open - dra in pulldowns produce a wired - and result). overdrive match rom [69 h]* the overdrive match rom command followed by a 64 - bit rom sequence transmitted at overdrive speed allows the bus master to address a specific ds28ec20 on a multidrop bus and to simultaneo usly set it in overdrive mode. only the ds28ec20 that exactly matches the 64 - bit rom sequence responds to the subsequent memory function command. slaves already in overdrive mode from a previous overdrive skip or successful overdrive match command remain i n overdrive mode. all overdrive - capable slaves return to standard speed at the next reset pulse of minimum 480s duration. the overdrive match rom command can be used with a single or multiple devices on the bus. * for operation at overdrive speed, the ds2 8ec20 requires v pup to be 5v 5%.
ds28ec20: 20k b 1- wire eeprom 19 of 27 figure 9 - 1. rom functions flow c hart y from figure 9, 2 nd part to memory functions flow chart ( figure 7) master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 ds28ec20 tx crc byte ds28ec20 tx serial number (6 bytes) ds28ec20 tx family code (1 byte) bit 0 match? y n bit 1 match? y n bit 63 match? y n ds28ec 20 tx bit 0 ds28ec20 tx bit 0 master tx bit 0 ds28ec20 tx bit 1 ds28ec20 tx bit 1 master tx bit 1 ds28ec20 tx bit 63 ds28ec20 tx bit 63 master tx bit 63 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n to figure 9, 2 nd part rc = 0 rc = 0 rc = 0 y y y n f0h search rom command? n 55h match rom command? n 33h read rom command? to figure 9, 2 nd part from memory functions flow chart ( figure 7 ) bus master tx rom function comm and ds28ec20 tx presence pulse od reset pulse? n y od = 0 bus master tx reset pulse from figure 9, 2 nd part rc = 0 n cch skip rom command?
ds28ec20: 20k b 1- wire eeprom 20 of 27 figure 9 - 2. rom functions flow c hart (continued) from figure 9, 1 st part from figure 9, 1 st part to figure 9, 1 st part rc = 1 ? n y rc = 0 ; od = 1 master tx bit 0 master tx bit 63 master tx bit 1 rc = 1 bit 0 match? y n bit 1 match? y n bit 63 match? y n y n 69h overdrive match rom? rc = 0 ; od = 1 master tx reset ? y n master tx reset ? n y y n 3ch overdrive skip rom? y n a5h resume command? to figure 9, 1 st part od = 0 od = 0 od = 0 1) 1) 1) 1) the od flag remains at 1 if the device was already at overdrive speed before the overdrive match rom command was issued. note : for operation at overdrive speed, the ds28ec20 requires v pup to be 5v 5%.
ds28ec20: 20kb 1-wire eeprom 21 of 27 1-wire signaling the ds28ec20 requires strict protocols to ensure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all falling edges. the ds28ec20 can communicate at two different speeds: standard speed and overdrive speed. if not expl icitly set into the overdrive mode, the ds28ec20 communicates at standard speed. while in overdrive mode th e fast timing applies to all waveforms. for operation at overdrive speed, t he ds28ec20 requires v pup to be 5v 5%. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 10 as ? , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1-wire network attached. the voltage v ilmax is relevant for the ds28ec20 when determining a logical level, not triggering any events. figure 10 shows the initialization se quence required to begin any communication with the ds28ec20. a reset pulse followed by a presence pulse indicates that the ds 28ec20 is ready to receive data, given the correct rom and memory function command. if the bus master uses slew -rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer exits the overdrive mode, returning the device to standard speed. if the ds28ec20 is in overdrive mode and t rstl is no longer than 80s, the device remains in overdrive mode. if the device is in overdrive mode and t rstl is between 80s and 480s, the device resets, but the communication speed is undetermined. figure 10. initialization proced ure: reset and presence pulse resistor master ds28ec20 t rstl t pdl t rsth t pdh master tx ?reset pulse? master rx ?presence pulse? v pup v ihmaster v th v tl v ilma x 0 v ? t f t rec t msp after the bus master has released the line it goes into receive mode. now the 1-wire bus is pulled to v pup through the pullup resistor, or in case of a ds2482-x00 or ds2480b driver, by active circuitry. when the threshold v th is crossed, the ds28ec20 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1-wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds28ec20 is ready for data communicati on. in a mixed population network, t rsth should be extended to minimum 480s at standard speed and 48s at overdrive sp eed to accommodate other 1-wire devices. read-/write-time slots data communication with the ds28ec20 takes place in time slots, which carry a single bit each. write-time slots transport data from bus master to slav e. read-time slots transfer data from slave to master. figure 11 illustrates the definitions of the writ e- and read-time slots. all communication begins with the master pulling the data lin e low. as the voltage on the 1-wire line falls below the threshold v tl , the ds28ec20 starts its internal timing genera tor that determines when the data line is sampled during a write-time slot and how long data is valid during a read-time slot.
ds28ec20: 20kb 1-wire eeprom 22 of 27 master-to-slave for a write-one time slot, the voltage on the data line must have crossed the v th threshold before the write-one low time t w1lmax is expired. for a write-zero time slot, t he voltage on the data line must stay below the v th threshold until the write-zero low time t w0lmin is expired. for the most reliable communication, the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds28ec20 needs a recovery time t rec before it is ready for the next time slot. figure 11. read/write timing diagram write-one time slot resistor master v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l ? write-zero time slot resistor master t rec v pup v ihmaster v th v tl v ilma x 0v t f t slot t w0l ? read-data time slot resistor master ds28ec20 t rec v pup v ihmaster v th v tl v ilma x 0v master sampling window ? t f t slot t rl t msr
ds28ec20: 20k b 1- wire eeprom 23 of 27 slave -to- master a read - data time slot begins like a write- one time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds28ec20 starts pulling the data line low; its internal timing generator dete rmines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds28ec20 does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the in ternal timing generator of the ds28ec20 on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds28ec20 to get ready for the next time slot. note that t rec specif ied herein applies only to a single ds28ec20 attached to a 1 - wire line. for multidevice configurations, t rec needs to be extended to accommodate the additional 1 - wire device input capacitance. alternatively, an interface that performs active pullup during the 1 - wire recovery time such as the ds2482 - x00 or ds2480b 1- wire line drivers can be used. improved network beh avior (switchpoint h ysteresis) in a 1 - wire environment, line termination is possible only during transients controlled by the bus master (1 - wi re driver). 1 - wire networks, therefore, are susceptible to noise of various origins. depending on the physical size and topology of the network, reflections from end points and branch points can add up or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1 - wire communication line. noise coupled onto the 1 - wire line from external sources can also result in signal glitching. a glitch during the rising edge of a time slot can cause a slave device to lose synchronizati on with the master and, consequently, result in a search rom command coming to a dead end or cause a device - specific function command to abort. for better performance in network applications, the ds28ec20 uses a new 1 - wire front - end, which makes it less se nsitive to noise. the 1 - wire front - end of the ds28ec20 differs from traditional slave devices in three characteristics: 1) there is additional low - pass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces th e sensitivity to high - frequency noise. this additional filtering does not apply at overdrive speed. 2) there is a hysteresis at the low -to - high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it is not recognized (f igure 12, case a). the hysteresis is effective at any 1 - wire speed. 3) there is a time window specified by the rising edge hold - off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 12, case b, t gl < t reh ). de ep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 12, case c, t gl t reh ). devices that have the parameters v hy and t reh specified in their electrical characteristics use the improved 1 - wire front -end. figure 12. noise suppression scheme v pup v th v hy 0v t reh t gl t reh t gl case a case c case b
ds28ec20: 20k b 1- wire eeprom 24 of 27 crc generation the ds28ec20 uses two different types of crcs. one crc is an 8 - bit type and is stored in the most significant byte of the 64 - bit rom. the bus master can compute a crc value from the first 56 bits of the 64- bit rom and compare it to the value stored within the ds28ec20 to determine if the rom data has been received error - free. the eq uivalent polynomial function of this crc is x 8 + x 5 + x 4 + 1. this 8 - bit crc is received in the true (noninverted) form. it is computed at the factory and programmed into the rom. the other crc is a 16 - bit type, generated according to the standard ized crc16 polynomial function x 16 + x 15 + x 2 + 1. this crc is used for fast verification of a data transfer when writing to or reading from the scratchpad and with the extended read memory command. in contrast to the 8 - bit crc, the 16- bit crc is always c ommunicated in the inverted form. a crc generator inside the ds28ec20 (figure 13) calculates a new 16- bit crc, as shown in the command flowchart (figure 7). the bus master compares the crc value read from the device to the one it calculates from the data, and decides whether to continue with an operation or to reread the portion of the data with the crc error . with the write scratchpad command, the crc is generated by first clearing the crc generator and then shifting in the command code, the ta rget addresses ta1 and ta2, and all the data bytes as they were sent by the bus master. the ds28ec20 transmits this crc only if the data bytes written to the scratchpad include scratchpad ending offset 11111b. the data can start at any location within the scratchpad. with the read scratchpad command, the crc is generated by first clearing the crc generator and then shifting in the command code, the target addresses ta1 and ta2, the e/s byte, and the scratchpad data as they were sent by the ds28ec20 startin g at the target address. the ds28ec20 transmits this crc only if the reading continues through the end of the scratchpad, regardless of the actual ending offset. with the initial pass through the extended read memory flow, the 16 - bit crc value is the res ult of shifting the command byte into the cleared crc generator, followed by the two address bytes and the data bytes. subsequent passes through the extended read memory flow generate a 16 - bit crc that is the result of clearing the crc generator and then s hifting in the data bytes . for more information on generating crc values refer to application note 27 : understanding and using cyclic redundancy checks with maxim i button products ( www.maxim - ic.com/an27 ). figure 13. crc16 hardware description and polynom ial polynomial = x 16 + x 15 + x 2 + 1 x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 x 9 x 10 x 11 x 12 x 13 x 14 x 15 x 16 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage 9 th stage 10 th stage 11 th stage 12 th stage 13 th stage 14 th stage 15 th stage 16 th stage input data crc output
ds28ec20: 20k b 1- wire eeprom 25 of 27 command - specific 1 -wire communication protoc ol legend symbol description rst 1 - wire reset pulse generated by master. pd 1 - wire presence pulse generated by slave. select command and data to satisfy the rom function pr otocol. ws command "write scratchpad". rs command "read scratchpad". cps command "copy scratchpad". rm command "read memory". erm command "extended read memory". ta target address ta1, ta2. ta - e/s target address ta1, ta2 with e/s byte. transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. transfer of as many data bytes as are needed to reach the end of the memory. transfer of as many data bytes as are needed to reach the end of the page for a given target address. crc16 \ transfer of an inverted crc16. ff loop indefinite loop where the master reads ff bytes. aa loop indefinite loop where the master reads aa bytes. programming data transfer to eeprom; no activ ity on the 1 - wire bus permitted during this time. command - specific 1 -wire communication protoc ol color codes master to slave slave to master programming write scratchpad (ca nnot fail) rst pd select ws ta crc16\ ff loop read scratch pad rst pd select rs ta - e/s crc16\ ff loop copy scratchpad (suc cess) rst pd select cps ta - e/s programming aa loop copy scratchpad (bs = 1 or pf = 1 or cop y protected) rst pd select cps ta - e/s ff loop
ds28ec20: 20k b 1- wire eeprom 26 of 27 read memory (cannot fail) rst pd select rm ta ff loop extended read memory (cannot fail) rst pd select erm ta crc16\ <32 bytes> crc16\ package information for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 6 tsoc d6+1 21 - 0382 90 - 0321 3 to - 92 (bulk) q3+1 21 - 0248 3 to - 92 (tape and reel) q3+4 21 - 0250 loop
ds28ec20: 20kb 1-wire eeprom 27 of 27 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 071007 initial release ? 1 091707 tsoc package added; corrected electrical characteristics table note 20 1, 4 2 040109 updated the text and graphics to mark which features are not applicable in the low-voltage environment 1, 3, 7, 11, 17, 18, 20, 21 created a second electrical characteristics table for 3.3v v pup (5%), operating temp range 0c to +70c, no overdrive 4, 5 3 11/11 removed information about the registration number being factory lasered into the chip in the general description section, 64-bit rom section, figure 3, and crc generation section 1, 7, 24 changed 125kbps to 90kbps in the features and hardware configuration sections 1, 16 updated the soldering information and added lead temperature information in the absolute maximum ratings section 2 updated the 5.0v/3.0v supply electrical characteristics tables parameters for c io , i l , t rec , t slot , i prog , and related notes 2?5 replaced the last sentence of the read memory [f0h] and extended read memory [a5h] sections to clarify the command 16 added the package information table 26 4 3/12 revised the 5.0v supply electrical characteristics table notes 1, 4, and 15 3 revised the 3.3v supply electrical characteristics table notes 3 and 14 5

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